In a computer system, transfers between devices such as processors, memories, input/output (I/O) units and other peripherals generally occur according to a protocol. These devices are commonly referred to as agents. The protocol is a method of handshaking that occurs between the devices during a transfer which allows each device involved in the transfer to know how the other device is going to act or perform.
Typically, transfers of data and information in a computer system are performed using multiple buses. These buses may be dedicated buses between only two devices or non-dedicated buses that are used by a number of units, bus agents or devices. Moreover, buses in the system may be dedicated to transferring a specific type of information. For instance, an address bus is used to transfer addresses, while a data bus is used to transfer data.
A bus transaction normally includes a requesting device, or agent, requesting data or a completion signal from another agent on the bus. The request usually includes some number of control signals indicating the type of request accompanied by the address of the desired data or the desired device. The device which is mapped into the address space containing the requested address responds by sending a completion signal along with any data as necessary.
In some computer systems, bus transactions occur in a pipelined manner. When bus transactions are pipelined, the requests from numerous bus agents are pending at the same time. This is possible due to the fact that separate data and address buses are used. In a pipelined transaction, while an address of a request is being sent on the address bus, the data or signals corresponding to a previously requested address (on the address bus) may be returned on the data bus. For example, if three requests are sent on the address bus, three responses occur on the data bus. In certain pipelined systems, the completion responses occur in the same order as they were requested. However, in other pipelined systems, the order of the completion responses does not have to occur in the same order as their corresponding requests. This type of bus system is commonly referred to as a split transaction bus system.
In split transaction buses, a bus transaction begins by initiating a request to one of the agents in the computer system. The response corresponding to the request is disassociated from the request completely. When the response is ready, the response initiates itself, thereby returning to the requesting agent in some manner. In one embodiment, the requests are tabbed so that they may be identified by the requesting agent upon their return.
In prior art computer systems, to accommodate split transactions, the systems require some capability of associating a data response with its address (i.e., its request). Typically, two separate token buses are used. When performing a request, an address is driven onto the address bus. At the same time, a token is driven on the first token bus. This token is associated with the address request. The token is received by the agent which is to respond to the address request (i.e., the responding agent). When the responding agent is ready to respond, the responding agent drives data, if necessary, onto the data bus. At the same time, the responding agent drives the same token on the second token bus. The requesting agent recognizes the token as the one that was associated with its original request, and in response, latches the data or signals to complete the bus transaction. Thus, in the prior art, a separate token bus is associated with the request path and another token bus is associated with the response path of a bus transaction.
Using two token buses increases the number of pins that are required to interface with the external bus. Prior art token buses normally are 8-bits in width. Therefore, using two separate token buses requires an additional sixteen pins to be added to the computer system, as well as additional space allocated on the computer board for the token buses. Moreover, the pins used to support the token buses must also be added to every bus agent package in the system. Thus, the cost of every package in the system increases. On the other hand, in a multi-processor system, the increase in bandwidth due to permitting split transactions is significant due to the ability to reorder long latency transactions behind short latency transactions issued later. It is desirable to reduce the cost of an integrated circuit chip package by reducing the number of pins required, yet still accommodate a split transaction bus arrangement.
The present invention provides a method and apparatus for implementing such a bus protocol. The protocol of the present invention provides a method and apparatus for accommodating split transactions across the external computer bus without the use of separate token buses and without an increased number of pins associated with them.